This processor was designed to illustrate how to create a simple processor in MAX+PlusII. For that reason there are only 4 registers, a few basic logic commands, only the most necessary flags, and only 64k bytes of addressable memory. It has an 8-bit data path and a 16-bit address space. This design scheme led to a single cycle RISC-like implementation. All memory accesses, besides instruction fetches use a concatenation of the A and B registers for the memory address. Because of the small number of registers, this processor is severely limited in its performance.
The instruction format is the standard "Opcode Operand, Operand". Load and Store currently do not operate correctly because of memory access conflicts with the IFU. The main design file contains the layout of the microprocessor, i.e., all the components and their interconnections. Each smaller component, the ALU for example, is in its own design file and might even be itself a collection of smaller units.

This design was first thought up for a computer architecture class which required a class project. As a result, the layout and general principles were learned in that class and not the result of trial and error or additional research. The layout is very basic and was designed at the same time that the opcodes were designated in an attempt to try to make them work well together. Although all of the architecture principles were learned in class, there was research needed to discover how a register operated and how to create one out of flip-flops. Because of the nature of the language, the entire design is structural. Everything is detailed down to the gate level. In the begining, I attempted to find a sample of some sort to help my learning of Max Plus, however, none were to be found. This resulted in my doing the entire design from scratch.

This projects represents the first layout for a microprocessor that I have done. It took some time getting use to the software and was interesting to learn that I could create a waveform for stimulus for the design. There were some snags along the way, including: having to use a larger model mode since the design grew so big, dealing with errors created by timing (this was almost impossible), and trying to  access memory for the operation and data access in the same cycle (this still has not been accompliched and may require either a second, out of phase clock or a multi-cycle design). There were many times in the process of actually laying out what I had envisioned that I realized there was; an easier way to do something. Hopefully all these painfull realizations will make my next design better.

A microprocessor with only 4 registers is almost useless. There would be too much main memory useage, and accessing main memory would require 2 of the registers for the address and one for data. This only leaves one register not involved in memory access. This would need to be addressed if this is ever redesigned.
 Lots of interconect wires running all over the screen can cause much confusion. Many times I made stupid and hard to find mistakes because I tapped into the wrong signal wire. This was especially true in the Control Logic because of its complexity and size. Microprocessor design is much less tedious and much easier when done visually then when done in a text based language such as VHDL. I have used VHDL software to design a much more complex 32 bit RISC multi-cycle microprocessor. The Max+Plus work seemed to go much faster and it was easier to see where everything was headed because I have an actual picture of my design in front of me rather then text which I had to interpret. However, VHDL allows for not only the structural type of designs, which would be described by a picture, but by procedural, which are more powerful and complex but cannot be turned into a schematic.
Download the Max+PlusII source code
Acknowledgement: This project was supported by a National Science Foundation Research Experience for Undergraduates Award.