VHDL generator for Dadda trees for multipliers and squaring circuits


 

For this project, I created code (in C++) to generate VHDL for a Dadda tree multiplier, VHDL for a Dadda tree squarer, and a GIF of the partial product reduction used in each.

You can use this link to a CGI program which will generate a GIF for you and send it to your browser window. - Temporarily unavailable.

Download the C++ source code

Acknowledgement: This project was supported by a National Science Foundation Research Experience for Undergraduates Award.


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