Louis Marquette's CAAR Related Files and Information

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The following projects have been completed as part of a National Science Foundation Research Experience for Undergraduates Project.

• A Simple 8-bit CPU designed in Max+PlusII
• A 32-bit DLX microprocessor designed and simulated in VHDL
• A VHDL generator for Dadda tree multiplies and squaring circuits
• A VHDL generator for array multipliers and reduced squaring arrays
• A squarer designed in Max Plus +
• A multiplyer array in Max Plus +

Applicable links:
   Altera - Maker of Max+PlusII, get an evaluation copy here to open GDF files.
 

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